A Reduced Complexity Low Voltage 1-Bit High-Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis

In this paper, a reduced complexity third-order digital delta-sigma modulator for fractional-N frequency synthesis is presented. The modulator consists of two sub-blocks and has a single bit output which makes it best for this application. A good shaping of quantization noise is achieved using a new architecture for a digital third-order delta-sigma modulator. The hardware required for this modulator is considerably less compared to previous works. The FPGA implementation of the whole system shows an SNR of 94dB and a dynamic range of 0.65 with an oversampling ratio of 167. The post-layout simulation of the digital circuit using 0.25μm CMOS technology predicts a maximum operating frequency of over 60MHz at a supply voltage of 1.5V.